Indium tin oxide (ITO) and fluorine-doped tin oxide (FTO or SnO:F) coatings are widely used as window electrodes in opto-electronic devices. These transparent conductive oxides (TCOs) have been immensely successful in a variety of applications. Unfortunately, however, the use of ITO and FTO is becoming increasingly problematic for a number of reasons. Such problems include, for example, the fact that there is a limited amount of the element indium available on Earth, the instability of the TCOs in the presence of acids or bases, their susceptibility to ion diffusion from ion conducting layers, their limited transparency in the near infrared region (e.g., the power-rich spectrum that may benefit some photovoltaic devices), high leakage current of FTO devices caused by FTO structure defects, etc. The brittle nature of ITO and its high deposition and/or processing temperature(s) can also limit its applications. In addition, surface asperities in SnO2:F may cause problematic arcing in some applications.
Thus, it will be appreciated that there is a need in the art for smooth and patternable electrode materials with good stability, high transparency, and excellent conductivity.
The search for novel electrode materials with good stability, high transparency, and excellent conductivity is ongoing. One aspect of this search involves identifying viable alternatives to such conventional TCOs. In this regard, the inventor of the instant invention has developed a viable transparent conductive coating (TCC) based on carbon and, more specifically, based on graphene.
The term graphene generally refers to one or more atomic layers of graphite, e.g., with a single graphene layer or SGL being extendible up to n-layers of graphite (e.g., where n can be as high as about 10, preferably about 5). Graphene's recent discovery and isolation (by cleaving crystalline graphite) comes at a time when the trend in electronics is to reduce the dimensions of the circuit elements to the nanometer scale. In this respect, graphene has unexpectedly led to a new world of unique opto-electronic properties, not encountered in standard electronic materials. This emerges from the linear dispersion relation (E vs. k), which gives rise to charge carriers in graphene having a zero rest mass and behaving like relativistic particles. The relativistic-like behavior of delocalized electrons moving around carbon atoms results from their interaction with the periodic potential of graphene's honeycomb lattice and gives rise to new quasi-particles that at low energies (E<1.2 eV) that are accurately described by the (2+1)-dimensional Dirac equation with an effective speed of light νF≈c/300=106 ms−1. Therefore, the well-established techniques of quantum electrodynamics (QED) (which deals with photons) can be brought to bear in the study of graphene—with a further advantageous aspect being that such effects are amplified in graphene by a factor of 300. For example, the universal coupling constant α is nearly 2 in graphene compared to 1/137 in vacuum. Moreover, it has been shown that graphene does not have any electronic band gap, which could open the door to novel opto-electronic applications.
Despite being only one-atom thick (at a minimum), graphene is chemically and thermally stable (although graphene may sometimes be surface-oxidized at 300 degrees C.), thereby allowing successfully fabricated graphene-based devices to withstand ambient and potentially harsh conditions. High quality graphene sheets were first made by micro-mechanical cleavage of bulk graphite. The same technique is being fine-tuned to currently provide high-quality graphene crystallites up to 100 μm2 in size. This size is sufficient for most research purposes in the micro-electronics field. Consequently, most techniques developed so far, mainly at universities, have focused more on the microscopic sample, and similarly have focused generally on device preparation and characterization rather than scaling up.
Unlike many current research trends, to realize the full potential of graphene as a possible TCC, large-area deposition of high quality material on substrates (e.g., silicon, glass, or plastic substrates, including coated versions of the same) is essential. To date, chemical vapor deposition (CVD) is seen by some as being the most promising process for the industrially viable large area growth of graphene. The accepted mechanism involves three steps, namely: (i) dissociation of the carbon precursor at high temperature (e.g., greater than 850 degrees C.) onto a polycrystalline metallic catalyst; (ii) carbon dissolution into the catalyst sub-surface; and (iii) graphene precipitation at the surface of the catalyst as the sample cools down.
Unfortunately, however, these techniques involve several drawbacks. First, they involve very high temperatures (e.g., greater than 850 degrees C. and sometimes higher than 950 degrees C.), as graphene quality is generally poor at lower temperatures since an amorphous graphitic carbon phase is always present given that the duration of the process is at least 30 minutes. Second, these techniques currently involve chemical etching of the catalyst for lift-off and transfer of the graphene onto the intended substrate. This process usually creases as well as contaminates the graphene film and, in general, is not scalable. The polycrystalline nature of the thick Ni, as well as its finite surface roughness, produces non-contiguous graphene domains of varying thickness (e.g., varying integer values of single layer graphene). This non-isotropic growth can be problematic for successful transfer and the fabrication of field effect devices based on graphene. Another characteristic of the incumbent process is that the catalyst film is a blanket film. But lift-off of a patterned thin film oftentimes causes the graphene to float and twist, making the transfer impractical.
Thus, it will be appreciated that it would be desirable to provide improved graphene-forming techniques, in terms of both scale and quality.
Certain example embodiments relate to a method of making a coated article including a graphene-inclusive thin film supported by a glass substrate. A layer comprising Si is formed on the substrate. A layer comprising Ni is formed on the layer comprising Si. Stress in the layer comprising Ni is engineered via He ion implantation and annealing. Following the engineering of stress, graphene is grown on both major surfaces of the layer comprising Ni via plasma-related chemical vapor deposition. The layer comprising Ni and the graphene on the major surface of the layer comprising Ni opposite the substrate are mechanically removed, with at least some of the graphene initially formed at the interface of the layer comprising Si and the layer comprising Ni remaining on the substrate on the layer comprising Si following the mechanical removal, in making the graphene-inclusive thin film.
Certain example embodiments relate to a method of making a coated article including a graphene-inclusive thin film supported by a glass substrate. A layer comprising Ni is formed on the substrate. He ions are implanted in the layer comprising Ni. The layer comprising Ni with the He ions implanted therein is heated. The implanting and the heating create a desired stress profile in the layer comprising Ni. Following creation of the desired stress profile in the layer comprising Ni, a hydrocarbon source gas and a separate hydrogen source gas are provided to a remote plasma-assisted chemical vapor deposition apparatus to facilitate graphene growth on major surfaces of the layer comprising Ni opposite the substrate and adjacent the substrate. The layer comprising Ni is delaminated from the substrate. The delamination removes the layer comprising Ni from the substrate together with graphene grown on the major surface of the layer comprising Ni opposite the substrate, while leaving on the substrate graphene grown on the major surface of the layer comprising Ni adjacent the substrate, in making the graphene-inclusive thin film.
Certain example embodiments relate to a method of making a coated article including a graphene-inclusive thin film supported by a glass substrate. A buffer layer is formed on the substrate. A metal catalyst layer is formed on the buffer layer. Stress in the metal catalyst layer is pre-engineered via He ion implantation and thermal annealing. Following the pre-engineering of stress, graphene is grown on both major surfaces of the metal catalyst layer using a remote plasma-assisted chemical vapor deposition apparatus operating in connection with separate hydrocarbon and hydrogen gasses provided at different flow rates and with a temperature of 450-550 degrees C. in no more than 10 minutes. The metal catalyst layer is removed from the substrate. The delamination removes the metal catalyst layer from the substrate together with graphene grown on the major surface of the metal catalyst layer opposite the substrate while leaving on the substrate graphene grown at the interface of the metal catalyst layer and the buffer layer, in making the graphene-inclusive thin film.
Articles made using these methods and products incorporating such articles also are contemplated herein. Windows, photovoltaic devices, displays, etc., are example applications that may benefit from the technology disclosed herein. In general, the techniques disclosed herein may be used anywhere a TCC would be desirable.
The features, aspects, advantages, and example embodiments described herein may be combined to realize yet further embodiments.